/**
 * *****************************************************************
 * @file    adt3102_utilities.c
 * @author  JiangQi(qijiang@andartechs.com.cn)
 * @version 1.0.0
 * @date    2021-05-07
 * @brief   
 *                 Copyright (c) 2021, Andar Technologies Inc.
 *                           www.andartechs.com 
 *
 * *****************************************************************
 */
/*------------------------------ include -------------------------------------*/
#include "adt3102.h"
#include "adt3102_utilities.h"
#include "adt3102_type_define.h"
#include "rfc_ctype_map.h"
#include "pmu_ctype_map.h"
#include "adt3102_system.h"
#include "adt3102_tx.h"


/*----------------------------- function -------------------------------------*/
/**
 * @brief   Set FMCW to single tone mode. Tone frequency is FMCW start frequency.
 * @param   None.
 * @return  None.
 * @note
 */
void fmcwChirpSingleFrequency(void)
{
  // set a single frequency, Only for test purpose.  
  // for example : 
  // FMCW_chirp(76,4000,346,20,0,32); //FMCW config Fstart ,FM , T0, T1, T2, chirp number; 
  // fmcwChirpSingleFrequency();   // then you will get a single frequency.
  RFC->fmcw_reg19_reg &= 0x0f ; //((ch0_df_step &0xF)<<4);// ch0 df_step
  RFC->fmcw_reg20_reg = 0x0 ;   //(ch0_df_step &0xFF)>>4; // ch0 df_step

  RFC->fmcw_reg24_reg &= 0x0f ; //((ch1_df_step &0xF)<<4);// ch1 df_step
  RFC->fmcw_reg25_reg = 0x0 ;   //(ch1_df_step &0xFF)>>4; // ch1 df_step

  RFC->fmcw_reg29_reg &= 0x0f ; //((ch2_df_step &0xF)<<4);// ch2 df_step
  RFC->fmcw_reg30_reg = 0x0 ;   //(ch2_df_step &0xFF)>>4; // ch2 df_step

  RFC->fmcw_reg18_reg &= 0xfd ; //ch0's clear [1] = 0. 
  RFC->fmcw_reg23_reg &= 0xfd ; //ch1's clear [1] = 0. 
  RFC->fmcw_reg28_reg &= 0xfd ; //ch2's clear [1] = 0. 
}


/**
 * @brief   Enable bist.
 * @param   bistSorSel: bist source select. 1 : from RF 0: from baseband.
 * @param   bistDivSel: bist divided frequency from 50MHz.
 * @return  None.
 * @note
 */
void bistOn(uint16 bistSorSel, uint16 bistDivSel)
{
    RFC->rfc_plli_ctrl_reg |= 1<<2;
    PMU->pmu_pmu_ctrl_reg |= pmu_pmu_ctrl_reg_manu_ctrl_en_bit;
    delayUs(100, HIGH_CLOCK);    
    PMU->pmu_pmu_ctrl_reg &= ~pmu_pmu_ctrl_reg_manu_ctrl_en_bit;
    
    biasBist(8, 8, 8, 8);
    
    if (bistSorSel == 1)
    {
        //BIST_EN_ONOFF_AMP ON
        RFC->rf_bist_cfg_reg = 0x07|bistDivSel<<8|0x01<<16|0x01<<24;
    }else
    {
        //BIST_RX0_ABB_EN BIST_RX1_ABB_EN ON
        RFC->rf_bist_cfg_reg = 0x35|bistDivSel<<8|0x01<<16|0x01<<24;
    }
    RFC->rf_bist_load = 1;
}

/**
 * @brief   select P27 as widen_bw signal, which is an indicator for CHIRP_T0.
            It will be 1 when transmit CHIRP_T0, and it is synchornized with CHIRP_T0.
            This signal could be used as an indicator synchornized with CHIRP_T0.
 * @param   None.
 * @return  None.
 * @note
 */
void widenBwP27(void)
{
    //disable en_buffer1 contorl for if signal output gpio27, 28, 29, 30.
    RFC->rfc_vga1_reg &= ~(1<<9);
    
    //set P27 as widen_bw signal. 
    *((uint32*)(GPIO_REGS + 27 + 12)) = 0x2 | 1<<9 | 1<<10 ;  //p27 as widen_bw. 
    
    //calculate T0's time. 
    uint32 widenBwWidth;
    widenBwWidth = (CHIRP_T0*1000)/8-1; //    
    RFC->fmcw_reg8_reg  = widenBwWidth & 0xff;
    RFC->fmcw_reg9_reg  = (widenBwWidth>>8) & 0xff;
    
    //assume the chirp is typical T0/T1/T2 chirp, so T0 would be channel 0. 
    RFC->fmcw_reg10_reg = 0x01;
    RFC->fmcw_reg11_reg = 0x0;  
}
